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In this paper, a new front end converter (FEC) topology has been proposed for the switched reluctance (SR) motor drive. This study aims to present the performance analysis of FEC-based SR motor drive using various types of control schemes like conventional proportional integral (PI) controller, fuzzy logic controller (FLC) and fuzzy-tuned proportional integral controller (Fuzzy-PI).

The proposed FEC-based SR motor drive with various control strategies is derived for the torque ripple minimization and speed control.

The steady state and the dynamic response of the FEC-based SR motor drive are analyzed using three different controllers under change in speed and loading conditions. The Fuzzy-PI-based control scheme improves the dynamic response of the system when compared with the FLC and the conventional PI controller.

The hardware prototype has been implemented for the FEC-based SR motor drive by using the Xilinx SPARTAN 6 FPGA processor. The experimental verification has been conducted and the results have been measured under steady state and dynamic conditions.

The main purpose of this paper is to propose a quasi-impedance source (QIS) converter fed switched reluctance motor (SRM) drive. The proposed converter topology is configured for DC link capacitance minimization and power factor (PF) correction.

A QIS converter is used as a front end converter to reduce the bulk capacitance requirement during current commutation and to decline the power ripple. To improve the PF with reduced total harmonic distortion at the input current, the PF current control loop is merged with the QIS converter control loop.

The overall SRM drive speed is regulated over a wide range by controlling the DC link voltage. The voltage regulation can be achieved by pulse width modulation of the QIS converter. Hence, the overall system efficiency has been improved by operating the proposed converter at a low switching frequency. Moreover, the proposed QIS converter uses an advanced repetitive controller to achieve voltage regulation and fewer ripples in torque.

The steady state and dynamic analyzes have been performed on the proposed drive topology. The performance of the proposed topology has been simulated through MATLAB/Simulink environment. A hardware prototype with a processor of Xilinx SPARTAN 6 field-programmable gate array has been used to validate the experimental response with the simulation results.