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The paper aims to investigate tool wear mechanism and tool geometry optimization of drilling PCB fixture hole.

An experimental study was carried out to investigate the chip formation and tool wear mechanism of drilling PCB fixture holes. Two types of drill with different types of chip-split groove were used in this study. The performances of these two types of drill bots were evaluated by tool wear and the shapes of chips.

The chips of drilling fixture holes contain aluminum chips from the cover board, copper chips from the copper foil, discontinuous glass fiber and resin from the CFRP. Feed rate and drilling speed have a great influence on the chip morphology. Abrasive wear of the drill lip is the main reason of the fixture drill bit in drilling PCB, and micro-chipping is observed on the tool nose and chisel edge. The influence of distance between the chip-split groove and drill point center on the axial force and torque is not obvious.

In this paper, hole wall roughness and drilling temperature were not analyzed in the optimization of drilling parameters. The future research work should consider them.

This paper investigated the mechanism of burr formation and tool wear in drilling of PCB fixture holes. Tool geometry was optimized by adding chip-split grooves.

The purpose of this paper was to investigate how variations in the geometry of silicon chips and the presence of surface defects affect their static bending properties. By comparing the bending radius and strength across differently sized and treated chips, the study sought to understand the underlying mechanics that contribute to the flexibility of silicon-based electronic devices. This understanding is crucial for the development of advanced, robust and adaptable electronic systems that can withstand the rigors of manufacturing and everyday use.

This study explores the impact of silicon chip geometry and surface defects on flexibility through a multifaceted experimental approach. The methodology included preparing silicon chips of three distinct dimensions and subjecting them to thinning processes to achieve a uniform thickness verified via scanning electron microscopy (SEM). Finite element method (FEM) simulations and a series of four-point bending tests were used to analyze the bending flexibility theoretically and experimentally. The approach was comprehensive, examining both the intrinsic geometric factors and the extrinsic influence of surface defects induced by manufacturing processes.

The findings revealed a significant deviation between the theoretical predictions from FEM simulations and the experimental outcomes from the four-point bending tests. Rectangular-shaped chips demonstrated superior flexibility, with smaller dimensions leading to an increased bending strength. Surface defects, identified as critical factors affecting flexibility, were analyzed through SEM and atomic force microscopy, showing that etching processes could reduce defect density and enhance flexibility. Notably, the study concluded that surface defects have a more pronounced impact on silicon chip flexibility than geometric factors, challenging initial assumptions and highlighting the need for defect minimization in chip manufacturing.

This research contributes valuable insights into the design and fabrication of flexible electronic devices, emphasizing the significant role of surface defects over geometric considerations in determining silicon chip flexibility. The originality of the work lies in its holistic approach to dissecting the factors influencing silicon chip flexibility, combining theoretical simulations with practical bending tests and surface defect analysis. The findings underscore the importance of optimizing manufacturing processes to reduce surface defects, thereby paving the way for the creation of more durable and flexible electronic devices for future technologies.

The purpose of this paper is to examine the quality of the turned surface. The quality of the surface produced depends on the nature of the chips, which are produced while turning metal matrix composites. This quality is a function of the machining parameters, tool material, tool configuration and elements of the composites.

In this study, the turning of AA7075/15 wt.% SiC (particle size 20–40 µm) composites is investigated. Thirty experiments were conducted, and the chip-formation mechanism in turning AA7075/SiCp composites at various combinations of cutting speeds, feed and depth of cuts was studied.

It is observed from the response surface methodology-based experimentation that in turning of coarser reinforcement (particle size 20–40 µm) composites, total gross fracture occurs. This causes small slices of chips and a higher shear plane angle. The nature of chips produced at various combinations of cutting speeds, feed and depth of cuts is different. The chips generated were segmented, spiral in cylindrical form, connected C type, chips with saw tooth, curled chips, washer C type chips, half-curved segmented chips and small-radii segmented chips.

The novelty of this research is that, so far, very little work has been published on the detailed analysis of chips produced during turning of AA7075/15 wt.% SiC (particle size 20–40 µm) composites.

The purpose of the study was to discover whether incorporating flours with high nutritive value along with pre-treatment of cereals with nixtamalization and sprouting of legumes would result in a high-quality healthy alternative for corn-based snacks.

Flours of nixtamalized cereals-corn, wheat, rice and sorghum and sprouted legumes-soybean and green gram are made into dough and baked instead of fried to form multi-grain chips. The particle size and physical properties of flour and nutritional, functional and textural properties of dough and chips are tested to study the effect of combination of nixtamalization of cereals and sprouting of legumes in the development of chips.

Baked multi-grain chips made of nixtamalized cereals and sprouted legumes had a significantly (p < 0.05) smaller particle size of 24.6 µm compared to T1 24.8 µm, C1 29.3 µm and C2 31.7 µm. T2 and C2 had significantly (p = 0.05) lower OAC value than C1 and T1 due to nixtamalization as nixtamalized flour needed half the amount of oil during dough formation. T1 showed highest calcium (mg/100 g) of 466 which was significantly (p < 0.05) higher than all other groups. The overall acceptability of T2 (8.6) was significantly (p < 0.05) higher than T1 (7.8), C2 (7.4) and C1 (6.8) on the nine-point Hedonic scale.

The developed chips are superior in terms of higher protein and minerals with better organoleptic acceptability and lower fat content in comparison to both corn chips and nixtamalized corn chips. The multi-grain chip therefore offers a new option for the consumer in high-quality healthy alternative to corn-based fried snacks.

The National Advisory Committee on Nutrition Education recently published a report containing long term dietary proposals. One of these is a reduction in fat consumption. Fats provide approximately 38% of the energy of an average British diet. This amounts to 110g fat daily in a diet with a total energy value of 2,500Kcal. It is recommended that this figure be reduced to 30% energy from fat, requiring a reduction in fat consumption of one quarter.

The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips.

Methods to embed chips in flex include flip‐chip assembly and subsequent lamination, or the construction of a separate ultra‐thin chip package (UTCP) using spin‐on polyimides and thin‐film metallisation technology. Thinning and separation of the chips is done using a “dicing‐by‐thinning” method.

The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 μm package where also the 20 μm thick chip is bendable.

Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demonstrators using the developed technologies.

Thinning down silicon chips to thicknesses of 25 μm and lower is an innovative technology, as well as assembly and embedding of these chips in flexible substrates.

As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost miniaturisation is flip‐chip assembly on FR4 boards. In this paper, two types of flip‐chip assembly process will be discussed: a process where flip‐chips with eutectic solder‐bumps are assembled by using a tacky flux, and a process where flip‐chips are assembled by using solder paste. Both processes have been verified on production boards, using production equipment. Demonstrated ppm defect levels are between 35 and 400 ppm (confidence level 95 per cent) at the solder joint level. Component yields for flip‐chips are between 99.2 and 100 per cent. The reliability of the assemblies fulfils consumer communication equipment requirements.

This study aims to investigate the effect of microtextured tools on the geometric morphology of serrated chips, and further improve the cutting performance of polycrystalline cubic boron nitride (PCBN) tool and extend the tool life and the surface quality of the machined surface.

A three-dimensional finite element cutting model of hardened steel AISI D2 with microtextured PCBN tools were established using the finite element software Abaqus, and cutting tests were carried out. Furthermore, the stress distribution in the primary deformation zone was investigated based on the triaxiality of stress, and the influence of microtexture on the geometric morphology of serrated chips and crack development was researched.

The results show that compared with nontexture tools, elliptical pits and wavy grooves microtexture tools have lower serrated degree Gs, higher serrated frequency f per unit length and more miniature serrated step Pc. The serrated phenomenon is intensified because the tensile stress zone of chips generated by nontextured tools is longer than that of elliptic pits and wavy grooves microtexture tools. Simultaneously, the maximum value of triaxiality in the tensile stress zone achieved by nontexture tools is larger than that of the two microtexture tools, and chips obtained by nontextured tools are more susceptible to propagation fractures.

This paper mainly studies the effect of microtexture on chip microgeometry, which is relatively little studied at present. At the same time, this paper has a certain engineering significance for PCBN tool turning hardening steel.

The peer review history for this article is available at: https://publons.com/publon/10.1108/ILT-05-2023-0149/

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

To determine the optimal chip/component placement for multi‐chip module (MCM) and printed circuit board (PCB) under thermal constraint.

The placement of power dissipating chips/component is carried out using genetic algorithms (GA) in order to achieve uniform thermal distribution on MCM and PCB. The thermal distribution on the MCM and PCB are predicted using 2D‐finite element method (FEM) analysis. Different number of chip/component and FEM meshing size is used to investigate the placement of chips/components.

The optimal placement of chip/component using GA is compared well to other placement techniques. The coarse meshing for FEM employed here is found adequate to carry out optimal placement of components by GA.

The analysis is valid for constant properties of MCM or PCB and steady state conditions. The chip/component size is limited to a single standard size.

The method is very useful for practical design of chip/component placement on MCM/PCB under thermal consideration.

FEM analyses of MCM and PCB can be easily implemented in the optimization procedure for obtaining the optimal chip/component placement based on thermal constraints.